HD74HC673 Datasheet | Hitachi Semiconductor

Description The HD74HC673 is a 16-bit shift register and a 16-bit storage register in a single 24-pin package. A threestate input/output (data I/O) port to the shift register allows serial entry and/or reading of data. The storage register is connected in a parallel data loop with the shift register and may be asynchronously cleared by taking the store-clear input low. The storage register may be parallel loaded with shift-register data to provide shift-register status via the parallel outputs. The shift register can be parallel loaded with the storage-register data upon mand. A high logic level at the chip-select (CS) input disables both the shift-register clock and the storage register clock and places the data I/O in the high-impedance state. The store-clear function is not disabled by the chip select. Caution must be exercised to prevent false clocking of either the shift register or the storage register via the chip-select input. The shift clock should be low during the low-to-high transition of chip select and the store clock should be low during the high-to-low transition of chip select. Features - - - - - High Speed Operation: tpd (MODE/STRCLK to Y) = 23 ns typ (C L = 50 p F) High Output Current: Fanout of 15 LSTTL Loads (Q15 output) Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs Mode/ CS H X L L L L L L R/W SHCLK X X L H H H H L X X X X STRCLR X L X X X L H H STRCLK X X X X L H H Z Q15 Q14n L Y15n Z Yes No Yes Yes Yes No No Yes Yes No Yes No No No Yes Yes No Yes No No No No No No No Yes SER/ Q15 Z Shift Register Functions Read from Write into Storage Register Parallel Functions Clear Load No Yes Shift Serial Output Serial Input Load No No No No Pin Arrangement CS SH CLK R/W STRCLR Mode/STRCLK SER/Q15 Y0 Y1 Y2 Y3 Y4 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 (Top...